The present invention relates to memory modules, particularly those containing memory devices that transmit and receive high speed pipelined signals.
Certain computer systems may employ a serial bus to transmit signals between a memory controller and memory. An example of such a serial bus has been defined by Rambus Corporation of Mountain View, Calif. That bus, often called the Direct Rambus memory channel, enables transmission of high speed, pipelined signals between a memory controller and memory. A memory card or module coupled to the bus may contain a number of high speed DRAMs, which have a Rambus developed architecture. Such memory devices are often called xe2x80x9cRambus DRAMsxe2x80x9d or xe2x80x9cRDRAMs.xe2x80x9d
The Direct Rambus memory channel requires signals to travel through all memory devices until terminated. Those memory devices add capacitance to the signal line, which lowers line impedance at those devices, when compared to the impedance of unloaded portions of the channel. That impedance discontinuity could adversely affect system performance, e.g., by requiring reduction in the maximum frequency at which high speed, pipelined electrical signals may be driven along the interconnectxe2x80x94to prevent signal reflection that may degrade signal quality.
To mitigate this effect, a design has been proposed in which the impedance of another portion of the signal line is raised to compensate for the reduced impedance at the memory devices. As shown in FIG. 1, which represents a printed circuit board (xe2x80x9cPCBxe2x80x9d) that contains several memory devices, relatively short high impedance lines 1 may be placed between memory devices 2 and unloaded portions 3 and 4 of the signal trace. (Dashed box 5 serves to indicate that PCB 10 may include memory devices in addition to those shown, which may be mounted to both sides of PCB 10. PCB 10 may, for example, include 16 memory devicesxe2x80x948 on each side.) Line 1 may provide an effective impedance of about 45 to 65 ohms. By adjusting the length of lines 1, the average impedance resulting from the combination of lines 1 and memory devices 2 (which constitutes the loaded portion of the channel) can closely match the impedance of the unloaded portions of the channel (e.g., unloaded portions 3 and 4 on PCB 10 and unloaded portions that are located on a motherboard designed to receive PCB 10). When the average impedance that results from combining lines 1 and memory devices 2 is approximately equal to that of the unloaded portions of the channel, (e.g., about 28 Ohms) the portion of the signal trace that lies between points 6 and 7 (i.e., the loaded portion of the channel) may, for all practical purposes, be treated as an extension of unloaded portions 3 and 4.
Because PCB 10 includes a trace that has relatively thin and relatively thick sections, PCB 10 requires that two impedance specifications be metxe2x80x94one for the high impedance portion of the trace (e.g., lines 1 of FIG. 1) and another for the unloaded portions of the trace (e.g., unloaded portions 3 and 4 of FIG. 1). Requiring a PCB to meet two different specifications for trace impedance may, however, increase cost and increase the amount of testing required to ensure that the PCB meets those specifications. In addition, requiring the PCB to meet two specifications may increase the failure rate, reducing yield. Accordingly, there is a need for a memory module that includes an improved mechanism for matching the impedance of the loaded portion of a signal trace with the impedance of the unloaded portion of that trace. There is a need for a memory module that maintains a uniform width for the trace as it is routed across the memory module, while still ensuring the impedance match.
A memory module is described. That memory module comprises a signal trace, which includes an unloaded portion and a loaded portion, and a memory device. The loaded portion has a first section and a second section, and the memory device has an input connection and an output connection. The first section of the loaded portion of the signal trace is coupled to the memory device""s input connection and the second section of the loaded portion of the signal trace is coupled to the memory device""s output connection. The impedance of the loaded portion is higher than it would have been if the first and second sections had been coupled to the same memory device connection.
In the following description, numerous specific details are set forth such as component types, dimensions, etc., to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.